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Maxim-Integrated /max32665 /DMA /INTR

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Interpret as INTR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (dis)CH0_IPEND 0 (CH1_IPEND)CH1_IPEND 0 (CH2_IPEND)CH2_IPEND 0 (CH3_IPEND)CH3_IPEND 0 (CH4_IPEND)CH4_IPEND 0 (CH5_IPEND)CH5_IPEND 0 (CH6_IPEND)CH6_IPEND 0 (CH7_IPEND)CH7_IPEND

CH0_IPEND=dis

Description

DMA Interrupt Register.

Fields

CH0_IPEND

Channel 0 Interrupt Pending.

0 (dis): Disable.

1 (en): Enable.
CH1_IPEND

Channel 1 Interrupt Pending.
CH2_IPEND

Channel 2 Interrupt Pending.
CH3_IPEND

Channel 3 Interrupt Pending.
CH4_IPEND

Channel 4 Interrupt Pending.
CH5_IPEND

Channel 5 Interrupt Pending.
CH6_IPEND

Channel 6 Interrupt Pending.
CH7_IPEND

Channel 7 Interrupt Pending.

Links

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Register Reference

https://github.com/analogdevicesinc/msdk