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Maxim-Integrated /max32665 /GCR /MEMCKCN

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Interpret as MEMCKCN

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0FWS0 (active)SYSRAM0LS 0 (SYSRAM1LS)SYSRAM1LS 0 (SYSRAM2LS)SYSRAM2LS 0 (SYSRAM3LS)SYSRAM3LS 0 (SYSRAM4LS)SYSRAM4LS 0 (SYSRAM5LS)SYSRAM5LS 0 (SYSRAM6LS)SYSRAM6LS 0 (ICACHELS)ICACHELS 0 (ICACHEXIPLS)ICACHEXIPLS 0 (SCACHELS)SCACHELS 0 (CRYPTOLS)CRYPTOLS 0 (USBLS)USBLS 0 (ROM0LS)ROM0LS 0 (ROM1LS)ROM1LS 0 (ICACHE1LS)ICACHE1LS

SYSRAM0LS=active

Description

Memory Clock Control Register.

Fields

FWS

Flash Wait State. These bits define the number of wait-state cycles per Flash data read access. Minimum wait state is 2.
SYSRAM0LS

System RAM 0 Light Sleep Mode.

0 (active): RAM is active.

1 (light_sleep): RAM is in Light Sleep mode.
SYSRAM1LS

System RAM 1 Light Sleep Mode.
SYSRAM2LS

System RAM 2 Light Sleep Mode.
SYSRAM3LS

System RAM 3 Light Sleep Mode.
SYSRAM4LS

System RAM 4 Light Sleep Mode.
SYSRAM5LS

System RAM 5 Light Sleep Mode.
SYSRAM6LS

System RAM 6 Light Sleep Mode.
ICACHELS

ICache RAM Light Sleep Mode.
ICACHEXIPLS

ICACHE-XIP RAM Light Sleep Mode.
SCACHELS

SysCache RAM Light Sleep Mode.
CRYPTOLS

CRYPTO RAM Light Sleep Mode.
USBLS

USB FIFO Light Sleep Mode.
ROM0LS

ROM Light Sleep Mode.
ROM1LS

ROM1 Light Sleep Mode.
ICACHE1LS

ICache RAM Light Sleep Mode.

Links

()

Register Reference

https://github.com/analogdevicesinc/msdk