SDHCFRQ=48MHz, AONCD=div_4
Peripheral Clock Divider.
| SDHCFRQ | SDHC Clock Frequency. This bits defines the clock frequency of SDHC. 0 (48MHz): undefined 1 (24MHz): undefined |
| ADCFRQ | ADC clock Frequency. These bits define the ADC clock frequency. FADC = FPCLK/(ADCFRQ). |
| AONCD | Always-ON(AON) domain CLock Divider. These bits define the AON domain clock divider. 0 (div_4): PCLK divide by 4. 1 (div_8): PCLK divide by 8. 2 (div_16): PCLK divide by 16. 3 (div_32): PCLK divide by 32. |