Maxim-Integrated /max32665 /GCR /PERCKCN1

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Interpret as PERCKCN1

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (en)BTLED 0 (en)UART2D 0 (TRNGD)TRNGD 0 (SCACHED)SCACHED 0 (SDMAD)SDMAD 0 (SMPHRD)SMPHRD 0 (SDHCD)SDHCD 0 (ICACHEXIPD)ICACHEXIPD 0 (OWIRED)OWIRED 0 (SPI0D)SPI0D 0 (SPIXIPDD)SPIXIPDD 0 (DMA1D)DMA1D 0 (AUDIOD)AUDIOD 0 (I2C2D)I2C2D 0 (HTMR0D)HTMR0D 0 (HTMR1D)HTMR1D 0 (WDT0D)WDT0D 0 (WDT1D)WDT1D 0 (WDT2D)WDT2D 0 (CPU1D)CPU1D

BTLED=en, UART2D=en

Description

Peripheral Clock Disable.

Fields

BTLED

BTLE Disable.

0 (en): Enable.

1 (dis): Disable.

UART2D

UART2 Disable.

0 (en): Enable.

1 (dis): Disable.

TRNGD

TRNG Disable.

SCACHED

System Cache Clock Disable.

SDMAD

SDMA Clock Disable.

SMPHRD

Semaphore Clock Disable.

SDHCD

SDHC/SDIO Clock Disable.

ICACHEXIPD

ICache XIP Clock Disable.

OWIRED

One-Wire Clock Disable.

SPI0D

SPI0 Clock Disable.

SPIXIPDD

SPI-XIP Data Clock Disable

DMA1D

DMA1 Clock Disable

AUDIOD

AUDIO Clock Disable

I2C2D

I2C 2 Clock Disable

HTMR0D

HTMR 0 Clock Disable

HTMR1D

HTMR 1 Clock Disable

WDT0D

WDT0 Clock Disable

WDT1D

WDT1 Clock Disable

WDT2D

WDT2 Clock Disable

CPU1D

CPU1 Clock Disable

Links

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