Maxim-Integrated /max32665 /GCR /RSTR1

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as RSTR1

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (reset_done)I2C1 0 (PT)PT 0 (SPIXIP)SPIXIP 0 (XSPIM)XSPIM 0 (SDHC)SDHC 0 (OWIRE)OWIRE 0 (WDT1)WDT1 0 (SPI0)SPI0 0 (SPIXMEM)SPIXMEM 0 (SMPHR)SMPHR 0 (WDT2)WDT2 0 (BTLE)BTLE 0 (AUDIO)AUDIO 0 (I2C2)I2C2 0 (RPU)RPU 0 (HTMR0)HTMR0 0 (HTMR1)HTMR1 0 (DVS)DVS 0 (SIMO)SIMO

I2C1=reset_done

Description

Reset 1.

Fields

I2C1

I2C1 Reset.

0 (reset_done): Reset complete.

1 (busy): Starts reset or indicates reset in progress.

PT

PT Reset.

SPIXIP

SPI XiP Master Reset.

XSPIM

GSPI XiP Master Controller Reset.

SDHC

SDHC/SDIO Reset.

OWIRE

OWIRE Reset.

WDT1

WDT1 Reset.

SPI0

SPI0 Reset.

SPIXMEM

SPIXMEM Reset.

SMPHR

SMPHR Reset.

WDT2

WDT2 Reset.

BTLE

BTLE Reset.

AUDIO

AUDIO Reset.

I2C2

I2C2 Reset.

RPU

RPU Reset.

HTMR0

HTMR0 Reset.

HTMR1

HTMR1 Reset.

DVS

DVS Reset.

SIMO

SIMO Reset.

Links

()