SBUSARB=fix, CCHK=complete, CHKRES=pass, OVR=0_9V, DCACHE_FLUSH=normal, CCACHE_FLUSH=normal, BSTAPEN=dis, SRCC_DIS=en, FLASH_PAGE_FLIP=normal
System Control.
| BSTAPEN | Boundary Scan TAP enable. When enabled, the JTAG port is connected to the Boundary Scan TAP. Otherwise, the port is connected to the ARM ICE function. This bit is reset by the POR. Reset value and access depend on the part number. 0 (dis): Boundary Scan TAP port disabled. 1 (en): Boundary Scan TAP port enabled. |
| SBUSARB | System bus abritration scheme. These bits are used to select between Fixed-burst abritration and Round-Robin scheme. The Round-Robin scheme is selected by default. These bits are reset by the system reset. 0 (fix): Fixed Burst abritration. 1 (round): Round-robin scheme. |
| FLASH_PAGE_FLIP | Flips the Flash bottom and top halves. (Depending on the total flash size, each half is either 256K or 512K). Initiating a flash page flip will cause a flush of both the data buffer on the DCODE bus and the internal instruction buffer. 0 (normal): Physical layout matches logical layout. 1 (swapped): Bottom half mapped to logical top half and vice versa. |
| CCACHE_FLUSH | Code Cache Flush. This bit is used to flush the code caches and the instruction buffer of the Cortex-M4. 0 (normal): Normal Code Cache Operation 1 (flush): Code Caches and CPU instruction buffer are flushed |
| DCACHE_FLUSH | Data Cache Flush. The system cache(s) will be flushed when this bit is set. 0 (normal): Normal System Cache Operation 1 (flush): System Cache is flushed |
| SRCC_DIS | SPIXR Cache Controller Disable. Disables the SRCC used for SPIXR code and data cache. Setting this field disables the cache and bypasses the cache line buffer. 0 (en): Is enabled. 1 (dis): Is Disabled. |
| CCHK | Compute ROM Checksum. This bit is self-cleared when calculation is completed. Once set, software clearing this bit is ignored and the bit will remain set until the operation is completed. 0 (complete): No operation/complete. 1 (start): Start operation. |
| CHKRES | ROM Checksum Result. This bit is only valid when CHKRD=1. 0 (pass): ROM Checksum Correct. 1 (fail): ROM Checksum Fail. |
| OVR | Operating Voltage Range. Setting these bits according to the VCore voltage allows the on-chip Random-Access memories to operate in their optimal timing range. 0 (0_9V): 0.9V +/- 10% 1 (1_0V): 1.0V +/- 10% 2 (1_1V): 1.1V +/- 10% |