WE=dis, ASE=dis, ALDF=inactive, ADE=dis, ALSF=inactive, RDYE=dis, RDY=busy, BUSY=idle, HTEN=dis
HTimer Control Register.
| HTEN | HTimer Enable. This bit enables the Real Time Clock. This bit can only be written when WE=1 and BUSY =0. Change to this bit is effective only after BUSY is cleared from 1 to 0. 0 (dis): Disable. 1 (en): Enable. |
| ADE | Long Interval Alarm Interrupt Enable. Change to this bit is effective only after BUSY is cleared from 1 to 0. 0 (dis): Disable. 1 (en): Enable. |
| ASE | Short Interval Alarm Interrupt Enable. Change to this bit is effective only after BUSY is cleared from 1 to 0. 0 (dis): Disable. 1 (en): Enable. |
| BUSY | HTimer Busy. This bit is set to 1 by hardware when changes to HTimer registers required a synchronized version of the register to be in place. This bit is automatically cleared by hardware. 0 (idle): Idle. 1 (busy): Busy. |
| RDY | HTimer Ready. This bit is set to 1 by hardware when the HTimer count registers update. It can be cleared to 0 by software at any time. It will also be cleared to 0 by hardware just prior to an update of the HTimer count register. 0 (busy): Register has not updated. 1 (ready): Ready. |
| RDYE | HTimer Ready Interrupt Enable. 0 (dis): Disable. 1 (en): Enable. |
| ALDF | Long Interval Alarm Interrupt Flag. This alarm is qualified as wake-up source to the processor. 0 (inactive): Not active 1 (pending): Active |
| ALSF | Short Interval Alarm Interrupt Flag. This alarm is qualified as wake-up source to the processor. 0 (inactive): Not active 1 (Pending): Active |
| WE | Write Enable. This register bit serves as a protection mechanism against unintentional writes to critical HTimer bits. 0 (dis): Not active 1 (en): Active |