Maxim-Integrated /max32665 /I2C0 /CTRL

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Interpret as CTRL

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (dis)I2C_EN 0 (slave_mode)MST 0 (dis)GEN_CALL_ADDR 0 (dis)RX_MODE 0 (ack)RX_MODE_ACK 0 (drive_scl_low)SCL_OUT 0 (drive_sda_low)SDA_OUT 0 (SCL)SCL 0 (SDA)SDA 0 (outputs_disable)SW_OUT_EN 0 (write)READ 0 (en)SCL_CLK_STRETCH_DIS 0 (dis)SCL_PP_MODE 0 (dis)HS_MODE

SDA_OUT=drive_sda_low, I2C_EN=dis, SCL_OUT=drive_scl_low, READ=write, GEN_CALL_ADDR=dis, MST=slave_mode, SCL_CLK_STRETCH_DIS=en, RX_MODE=dis, RX_MODE_ACK=ack, HS_MODE=dis, SW_OUT_EN=outputs_disable, SCL_PP_MODE=dis

Description

Control Register.

Fields

I2C_EN

I2C Enable.

0 (dis): Disable I2C.

1 (en): enable I2C.

MST

Master Mode Enable.

0 (slave_mode): Slave Mode.

1 (master_mode): Master Mode.

GEN_CALL_ADDR

General Call Address Enable.

0 (dis): Ignore Gneral Call Address.

1 (en): Acknowledge general call address.

RX_MODE

Interactive Receive Mode.

0 (dis): Disable Interactive Receive Mode.

1 (en): Enable Interactive Receive Mode.

RX_MODE_ACK

Data Acknowledge. This bit defines the acknowledge bit returned by the I2C receiver while IRXM = 1 HW forces ACK to 0 when IRXM = 0.

0 (ack): return ACK (pulling SDA LOW).

1 (nack): return NACK (leaving SDA HIGH).

SCL_OUT

SCL Output. This bits control SCL output when SWOE =1.

0 (drive_scl_low): Drive SCL low.

1 (release_scl): Release SCL.

SDA_OUT

SDA Output. This bits control SDA output when SWOE = 1.

0 (drive_sda_low): Drive SDA low.

1 (release_sda): Release SDA.

SCL

SCL status. This bit reflects the logic gate of SCL signal.

SDA

SDA status. THis bit reflects the logic gate of SDA signal.

SW_OUT_EN

Software Output Enable.

0 (outputs_disable): I2C Outputs SCLO and SDAO disabled.

1 (outputs_enable): I2C Outputs SCLO and SDAO enabled.

READ

Read. This bit reflects the R/W bit of an address match (AMI = 1) or general call match(GCI = 1). This bit is valid 3 cycles after the relevant interrupt bit is set.

0 (write): Write.

1 (read): Read.

SCL_CLK_STRETCH_DIS

This bit will disable slave clock stretching when set.

0 (en): Slave clock stretching enabled.

1 (dis): Slave clock stretching disabled.

SCL_PP_MODE

SCL Push-Pull Mode. This bit controls whether SCL is operated in a the I2C standard open-drain mode, or in a non-standard push-pull mode where the Hi-Z output isreplaced with Drive-1. The non-standard mode should only be used when operating as a master and communicating with slaves that are guaranteed to never drive SCL low.

0 (dis): Standard open-drain operation: drive low for 0, Hi-Z for 1

1 (en): Non-standard push-pull operation: drive low for 0, drive high for 1

HS_MODE

Hs-mode Enable.

0 (dis): Hs-mode disabled.

1 (en): Hs-mode enabled.

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