TX_READY_MODE=en, TX_FLUSH=not_flushed
Transmit Control Register 0.
| TX_PRELOAD | Transmit FIFO Preaload Mode. Setting this bit will allow for high speed application to preload the transmit FIFO prior to Slave Address Match. |
| TX_READY_MODE | Transmit FIFO Ready Manual Mode. 0 (en): HW control of I2CTXRDY enabled. 1 (dis): HW control of I2CTXRDY disabled. |
| TX_AMGC_AFD | TX FIFO General Call Address Match Auto Flush. |
| TX_AMW_AFD | TX FIFO Slave Address Match Write Auto Flush. |
| TX_AMR_AFD | TX FIFO Slave Address Match Read Auto Flush. |
| TX_NACK_AFD | TX FIFO received NACK Auto Flush. |
| TX_FLUSH | Transmit FIFO Flush. This bit is automatically cleared to 0 after the operation. 0 (not_flushed): FIFO not flushed. 1 (flush): Flush TX_FIFO. |
| TX_THRESH | Transmit FIFO Threshold. These bits define the TX_FIFO interrupt threshold. |