WE=inactive, ACRE=sync, SQE=inactive, BUSY=idle, FT=freq1Hz, ALDF=inactive, RTCE=dis, ALSF=inactive, ASE=dis, RDYE=dis, ADE=dis, RDY=busy
RTC Control Register.
| RTCE | Real Time Clock Enable. This bit enables the Real Time Clock. This bit can only be written when WE=1 and BUSY =0. Change to this bit is effective only after BUSY is cleared from 1 to 0. 0 (dis): Disable. 1 (en): Enable. |
| ADE | Alarm Time-of-Day Interrupt Enable. Change to this bit is effective only after BUSY is cleared from 1 to 0. 0 (dis): Disable. 1 (en): Enable. |
| ASE | Alarm Sub-second Interrupt Enable. Change to this bit is effective only after BUSY is cleared from 1 to 0. 0 (dis): Disable. 1 (en): Enable. |
| BUSY | RTC Busy. This bit is set to 1 by hardware when changes to RTC registers required a synchronized version of the register to be in place. This bit is automatically cleared by hardware. 0 (idle): Idle. 1 (busy): Busy. |
| RDY | RTC Ready. This bit is set to 1 by hardware when the RTC count registers update. It can be cleared to 0 by software at any time. It will also be cleared to 0 by hardware just prior to an update of the RTC count register. 0 (busy): Register has not updated. 1 (ready): Ready. |
| RDYE | RTC Ready Interrupt Enable. 0 (dis): Disable. 1 (en): Enable. |
| ALDF | Time-of-Day Alarm Interrupt Flag. This alarm is qualified as wake-up source to the processor. 0 (inactive): Not active 1 (Pending): Active |
| ALSF | Sub-second Alarm Interrupt Flag. This alarm is qualified as wake-up source to the processor. 0 (inactive): Not active 1 (Pending): Active |
| SQE | Square Wave Output Enable. 0 (inactive): Not active 1 (Pending): Active |
| FT | Frequency Output Selection. When SQE=1, these bits specify the output frequency on the SQW pin. 0 (freq1Hz): 1 Hz (Compensated). 1 (freq512Hz): 512 Hz (Compensated). 2 (freq4KHz): 4 KHz. 3 (clkDiv8): RTC Input Clock / 8. |
| ACRE | Asynchronous Counter Read Enable. 0 (sync): SEC and SSEC registers synchronized and should only be accessed while CTRL.rdy = 1. 1 (async): SEC and SSEC registers are asynchronous and will require software interaction to ensure data accuracy. |
| WE | Write Enable. This register bit serves as a protection mechanism against unintentional writes to critical RTC bits. 0 (inactive): Not active 1 (Pending): Active |