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Maxim-Integrated /max32665 /SDHC /CFG_0

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Interpret as CFG_0

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0CLK_FREQ0 (TO_CLK_UNIT)TO_CLK_UNIT 0TO_CLK_FREQ0MAX_BLK_LEN 0 (BIT_8)BIT_8 0 (ADMA2)ADMA2 0 (HS)HS 0 (SDMA)SDMA 0 (SUSPEND)SUSPEND 0 (V3_3)V3_3 0 (V3_0)V3_0 0 (V1_8)V1_8 0 (BIT_64_SYS_BUS)BIT_64_SYS_BUS 0 (ASYNC_INT)ASYNC_INT 0SLOT_TYPE

Description

Capabilities 0-31.

Fields

CLK_FREQ

Timeout Clock Frequency.
TO_CLK_UNIT

Timeout Clock Unit.
TO_CLK_FREQ

Base Clock Frequency For SD Clock.
MAX_BLK_LEN

Max Block Length.
BIT_8

8-bit Support for Embedded Device.
ADMA2

ADMA2 Support.
HS

High Speed Support.
SDMA

SDMA Support.
SUSPEND

Suspend/Resume Support.
V3_3

Voltage Support 3.3V.
V3_0

Voltage Support 3.0V.
V1_8

Voltage Support 1.8V.
BIT_64_SYS_BUS

64-bit System Bus Support.
ASYNC_INT

Asynchronous Interrupt Support.
SLOT_TYPE

Slot Type.

Links

()

Register Reference

https://github.com/analogdevicesinc/msdk