MODE=SPIX_Mode_0, PAGE_SIZE=4_bytes, SS_ACT=0_CLKS, LO_CLK=16_SCLK, HI_CLK=16_SCLK, SS_INACT=4_CLKS, SSEL=Slave_0
Configuration Register.
| SSEL | Slaves Select. 0 (Slave_0): Slave 0 is selected. 1 (Slave_1): Slave 1 is selected. |
| MODE | Defines SPI Mode, Only valid values are 0 and 3. 0 (SPIX_Mode_0): SPIX Mode 0. CLK Polarity = 0, CLK Phase = 0. 3 (SPIX_Mode_3): SPIX Mode 3. CLK Polarity = 1, CLK Phase = 1. |
| PAGE_SIZE | Page Size. 0 (4_bytes): 4 bytes. 1 (8_bytes): 8 bytes. 2 (16_bytes): 16 bytes. 3 (32_bytes): 32 bytes. |
| HI_CLK | SCLK High Clocks. Number of system clocks that SCLK will be high when SCLK pulses are generated. 0 Correspond to 16 system clocks and, all other values defines the number of system clock taht SCLK will be held high. 0 (16_SCLK): 16 system clocks. |
| LO_CLK | SCLK low Clocks. Number of system clocks that SCLK will be low when SCLK pulses are generated. 0 correspond to 16 system clocks and, all other values defines the number of system clock taht SCLK will be held low. 0 (16_SCLK): 16 system clocks. |
| SS_ACT | Slaves Select Activate Timing. 0 (0_CLKS): 0 sytem clocks. 1 (2_CLKS): 2 sytem clocks. 2 (4_CLKS): 4 sytem clocks. 3 (8_CLKS): 8 sytem clocks. |
| SS_INACT | Slaves Select Inactive Timing. 0 (4_CLKS): 4 sytem clocks. 1 (6_CLKS): 6 sytem clocks. 2 (8_CLKS): 8 sytem clocks. 3 (12_CLKS): 12 sytem clocks. |
| IOSMPL | Sample Delay. |