SCKFBINV=Dis, SCLK_FB=Dis, BB_DATA_OUT_EN=SDIO0, SCLK_DR=SCLK_0, SSDR=output0, BBMODE=dis, RX_FIFO_EN=DIS_RXFIFO, SDIO_DATA_IN=SDIO0, BB_DATA=SDIO0, TX_FIFO_EN=dis_txfifo, ENABLE=dis, SMPLSS=Dis, SIMPLERX=Dis, SIMPLE=Dis
SPIX Controller General Controller Register.
| ENABLE | SPI Master enable. 0 (dis): Disable SPI Master, putting a reset state. 1 (en): Enable SPI Master for processing transactions. |
| TX_FIFO_EN | Transaction FIFO Enable. 0 (dis_txfifo): Disable Transaction FIFO. 1 (en_txfifo): Enable Transaction FIFO. |
| RX_FIFO_EN | Result FIFO Enable. 0 (DIS_RXFIFO): Disable Result FIFO. 1 (EN_RXFIFO): Enable Result FIFO. |
| BBMODE | Bit-Bang Mode. 0 (dis): Disable Bit-Bang Mode. 1 (en): Enable Bit-Bang Mode. |
| SSDR | This bits reflects the state of the currently selected slave select. 0 (output0): Selected Slave select output = 0. 1 (output1): Selected Slave select output = 1. |
| SCLK_DR | SSCLK Drive and State. 0 (SCLK_0): SCLK is 0. 1 (SCLK_1): SCLK is 1. |
| SDIO_DATA_IN | SDIO Input Data Value. 0 (SDIO0): SDIO[0] 1 (SDIO1): SDIO[1] 2 (SDIO2): SDIO[2] 3 (SDIO3): SDIO[3] |
| BB_DATA | No description available. 0 (SDIO0): SDIO[0] 1 (SDIO1): SDIO[1] 2 (SDIO2): SDIO[2] 3 (SDIO3): SDIO[3] |
| BB_DATA_OUT_EN | Bit Bang SDIO Output Enable. 0 (SDIO0): SDIO[0] 1 (SDIO1): SDIO[1] 2 (SDIO2): SDIO[2] 3 (SDIO3): SDIO[3] |
| SIMPLE | Simple Mode Enable. 0 (Dis): undefined 1 (En): undefined |
| SIMPLERX | Simple Receive Enable. 0 (Dis): undefined 1 (En): undefined |
| SMPLSS | Simple Mode Slave Select. 0 (Dis): undefined 1 (En): undefined |
| SCLK_FB | Enable SCLK Feedback Mode. 0 (Dis): undefined 1 (En): undefined |
| SCKFBINV | SCK Inversion. 0 (Dis): undefined 1 (En): undefined |