SCLKINH3=EN, SDIOOE=SDIO0, SDIOOUT=SDIO0, SAMPL=Dis
SPIX Controller Special Control Register.
| SAMPL | SDIO Sample Mode Enable. 0 (Dis): undefined 1 (En): undefined |
| SDIOOUT | SDIO Output Value Sample Mode. 0 (SDIO0): SDIO[0] 1 (SDIO1): SDIO[1] 2 (SDIO2): SDIO[2] 3 (SDIO3): SDIO[3] |
| SDIOOE | SDIO Output Enable Sample Mode. 0 (SDIO0): SDIO[0] 1 (SDIO1): SDIO[1] 2 (SDIO2): SDIO[2] 3 (SDIO3): SDIO[3] |
| SCLKINH3 | SCLK Inhibit Mode3. In SPI Mode 3, some SPI flash read timing diagrams show the last SCLK going low prior to de-assertion. The default is to support this additional falling edge of clock. When this bit is set and the device is in SPI Mode 3, the SPI clock is held high while Slave Select is de-asserted. This is to support some SPI flash write timing diagrams. 0 (EN): Allow trailing SCLK low pulse prior to Slave Select de-assertion. 1 (DIS): Inhibit trailing SCLK low pulse prior to Slave Select de-assertion. |