SS_CTRL=deassert, TIMER=dis, MMEN=dis, SSIO=output, SPIEN=dis, FL_EN=dis
Register for controlling SPI peripheral.
| SPIEN | SPI Enable. 0 (dis): SPI is disabled. 1 (en): SPI is enabled. |
| MMEN | Master Mode Enable. 0 (dis): SPI is Slave mode. 1 (en): SPI is Master mode. |
| TIMER | Timer Enable. 0 (dis): Timer is disabled. 1 (en): Timer is enabled, only valid if SPIEN=0. |
| FL_EN | Flow Control Mode Enable. 0 (dis): Flow Control mode is disabled. 1 (en): Flow Control Mode is enabled. |
| SSIO | Slave Select 0, IO direction, to support Multi-Master mode, Slave Select 0 can be input in Master mode. This bit has no effect in slave mode. 0 (output): Slave select 0 is output. 1 (input): Slave Select 0 is input, only valid if MMEN=1. |
| TX_START | Start Transmit. 1 (start): Master Initiates a transaction, this bit is self clearing when transactions are done. If a transaction completes, and the TX FIFO is empty, the Master halts, if a transaction completes, and the TX FIFO is not empty, the Master initiates another transaction. |
| SS_CTRL | Slave Select Control. 0 (deassert): SPI de-asserts Slave Select at the end of a transaction. 1 (assert): SPI leaves Slave Select asserted at the end of a transaction. |
| SS | Slave Select, when in Master mode selects which Slave devices are selected. More than one Slave device can be selected. 1 (SS0): SS0 is selected. 2 (SS1): SS1 is selected. 4 (SS2): SS2 is selected. 8 (SS3): SS3 is selected. 16 (SS4): SS4 is selected. 32 (SS5): SS5 is selected. 64 (SS6): SS6 is selected. 128 (SS7): SS7 is selected. |