NUMBITS=0, THREE_WIRE=dis, DATA_WIDTH=Mono, SCLK_FB_INV=NON_INV
Register for controlling SPI peripheral.
| CPHA | Clock Phase. |
| CPOL | Clock Polarity. |
| SCLK_FB_INV | Invert SCLK Feedback in Master Mode. 0 (NON_INV): SCLK is not inverted to Line Receiver. 1 (INV): SCLK is inverted to Line Receiver. |
| NUMBITS | Number of Bits per character. 0 (0): 16 bits per character. |
| DATA_WIDTH | SPI Data width. 0 (Mono): 1 data pin. 1 (Dual): 2 data pins. 2 (Quad): 4 data pins. |
| THREE_WIRE | Three Wire mode. MOSI/MISO pin(s) shared. Only Mono mode suports Four-Wire. 0 (dis): Use four wire mode (Mono only). 1 (en): Use three wire mode. |
| SSPOL | Slave Select Polarity, each Slave Select can have unique polarity. 1 (SS0_high): SS0 active high. 2 (SS1_high): SS1 active high. 4 (SS2_high): SS2 active high. 8 (SS3_high): SS3 active high. 16 (SS4_high): SS4 active high. 32 (SS5_high): SS5 active high. 64 (SS6_high): SS6 active high. 128 (SS7_high): SS7 active high. |