Register for reading and clearing interrupt flags. All bits are write 1 to clear.
| TX_THRESH | TX FIFO Threshold Crossed. 1 (clear): Flag is set when value read is 1. Write 1 to clear this flag. |
| TX_EMPTY | TX FIFO Empty. 1 (clear): Flag is set when value read is 1. Write 1 to clear this flag. |
| RX_THRESH | RX FIFO Threshold Crossed. 1 (clear): Flag is set when value read is 1. Write 1 to clear this flag. |
| RX_FULL | RX FIFO FULL. 1 (clear): Flag is set when value read is 1. Write 1 to clear this flag. |
| SSA | Slave Select Asserted. 1 (clear): Flag is set when value read is 1. Write 1 to clear this flag. |
| SSD | Slave Select Deasserted. 1 (clear): Flag is set when value read is 1. Write 1 to clear this flag. |
| FAULT | Multi-Master Mode Fault. 1 (clear): Flag is set when value read is 1. Write 1 to clear this flag. |
| ABORT | Slave Abort Detected. 1 (clear): Flag is set when value read is 1. Write 1 to clear this flag. |
| M_DONE | Master Done, set when SPI Master has completed any transactions. 1 (clear): Flag is set when value read is 1. Write 1 to clear this flag. |
| TX_OVR | Transmit FIFO Overrun, set when the AMBA side attempts to write data to a full transmit FIFO. 1 (clear): Flag is set when value read is 1. Write 1 to clear this flag. |
| TX_UND | Transmit FIFO Underrun, set when the SPI side attempts to read data from an empty transmit FIFO. 1 (clear): Flag is set when value read is 1. Write 1 to clear this flag. |
| RX_OVR | Receive FIFO Overrun, set when the SPI side attempts to write to a full receive FIFO. 1 (clear): Flag is set when value read is 1. Write 1 to clear this flag. |
| RX_UND | Receive FIFO Underrun, set when the AMBA side attempts to read data from an empty receive FIFO. 1 (clear): Flag is set when value read is 1. Write 1 to clear this flag. |