WAIT_POL=activeLo, DMADNE_MSK=not_used, FLAG_MODE=unres_wr, DMA_DONE=notDone, RDY=busy, RST=reset_done, ERR=noError, SRC=inputFIFO, INT=dis, RDSRC=dmaDisabled, WRSRC=none
Crypto Control Register.
| RST | Reset. This bit is used to reset the crypto accelerator. All crypto internal states and related registers are reset to their default reset values. Control register such as CRYPTO_CTRL, CIPHER_CTRL, HASH_CTRL, CRC_CTRL, MAA_CTRL (with the exception of the STC bit), HASH_MSG_SZ_[3:0] and MAA_MAWS will retain their values. This bit will automatically clear itself after one cycle. 0 (reset_done): Reset complete. 1 (busy): Reset in progress. 1 (reset): Starts reset operation. |
| INT | Interrupt Enable. Generates an interrupt when done or error set. 0 (dis): Disable 1 (en): Enable |
| SRC | Source Select. This bit selects the hash function and CRC generator input source. 0 (inputFIFO): Input FIFO 1 (outputFIFO): Output FIFO |
| BSO | Byte Swap Output. Note. No byte swap will occur if there is not a full word. |
| BSI | Byte Swap Input. Note. No byte swap will occur if there is not a full word. |
| WAIT_EN | Wait Pin Enable. This can be used to hold off the crypto DMA until an external memory is ready. This is useful for transferring pages from NAND flash which may take several microseconds to become ready. |
| WAIT_POL | Wait Pin Polarity. When the wait pin is enabled, this bit selects its active state. 0 (activeLo): Active Low. 1 (activeHi): Active High. |
| WRSRC | Write FIFO Source Select. This field determines where data written to the write FIFO comes from. When data is written to the write FIFO, it is always written out the DMA. To decrypt or encrypt data, the write FIFO source should be set to the cipher output. To implement memcpy() or memset() functions, or to fill memory with random data, the write FIFO source should be set to the read FIFO. When calculating a HASH or CMAC, the write FIFO should be disabled. 0 (none): None. 1 (cipherOutput): Cipher Output. 2 (readFIFO): Read FIFO. |
| RDSRC | Read FIFO Source Select. This field selects the source of the read FIFO. Typically, it is set to use the DMA. To implement a memset() function, the read FIFO DMA should be disabled. To fill memory with random data or to hash random numbers, the read FIFO source should be set to the random number generator. 0 (dmaDisabled): DMA Disable. 1 (dmaOrApb): DMA Or APB. 2 (rng): RNG. |
| FLAG_MODE | Done Flag Mode. This bit configures the access behavior of the individual CRYPTO_CTRL Done flags (CRYPTO_CTRL[27:24]). This bit is cleared only on reset to limit upkeep, i.e. once set, it will remain set until a reset occurs. 0 (unres_wr): Unrestricted write (0 or 1) of CRYPTO_CTRL[27:24] flags. 1 (res_wr): Access to CRYPTO_CTRL[27:24] are write 1 to clear/write 0 no effect. |
| DMADNE_MSK | DMA Done Flag Mask. This bit masks the DMA_DONE flag from being used to generate the CRYPTO_CTRL.DONE flag, and this disables a DMA_DONE condition from generating and interrupt. The DMA_DONE flag itself is unaffected and still may be monitored. This allows more optimal interrupt-driven crypto operations using DMA. 0 (not_used): DMA_DONE not used in setting CRYPTO_CTRL.DONE bit. 1 (used): DMA_DONE used in setting CRYPTO_CTRL.DONE bit. |
| DMA_DONE | DMA Done. DMA write/read operation is complete. This bit must be cleared before starting a DMA operation. 0 (notDone): Not Done. 1 (done): Done. |
| GLS_DONE | Galois Done. FIFO is full and CRC or Hamming Code Generator is enabled. This bit must be cleared before starting a CRC operation Note that DMA_DONE must be polled instead of this bit to determine the end of DMA operation during the utilization of Hamming Code Generator. |
| HSH_DONE | Hash Done. SHA operation is complete. This bit must be cleared before starting a HASH operation. |
| CPH_DONE | Cipher Done. Either AES or DES encryption/decryption operation is complete. This bit must be cleared before starting a cipher operation. |
| MAA_DONE | MAA Done. MAA operation is complete. This bit must be cleared before starting a new MAA operation. This bit is read only while the MAA is in progress. This bit is negate of MAA_CTRL.STC. |
| ERR | AHB Bus Error. This bit is set when the DMA encounters a bus error during a read or write operation. Once this bit is set, the DMA will stop. This bit can only be cleared by resetting the crypto block. 0 (noError): No Error. 1 (error): Error. |
| RDY | Ready. Crypto block ready for more data. 0 (busy): Busy. 1 (ready): Ready. |
| DONE | Done. One or more cryptographic calculations complete (logical OR of done flags). |