Maxim-Integrated /max32665 /UART0 /CTRL

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Interpret as CTRL

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (dis)ENABLE 0 (dis)PARITY_EN 0 (Even)PARITY 0 (1)PARMD 0 (TX_FLUSH)TX_FLUSH 0 (RX_FLUSH)RX_FLUSH 0 (FRAME)BITACC 0 (5)CHAR_SIZE 0 (1)STOPBITS 0 (dis)FLOW_CTRL 0 (0)FLOW_POL 0 (DIS)NULL_MODEM 0 (DIS)BREAK 0 (SYSTEM)CLKSEL 0RX_TO

BREAK=DIS, CLKSEL=SYSTEM, STOPBITS=1, PARITY_EN=dis, ENABLE=dis, NULL_MODEM=DIS, PARITY=Even, CHAR_SIZE=5, FLOW_CTRL=dis, PARMD=1, FLOW_POL=0, BITACC=FRAME

Description

Control Register.

Fields

ENABLE

UART enabled, to enable UART block, it is used to drive a gated clock in order to save power consumption when UART is not used. FIFOs are flushed when UART is disabled.

0 (dis): UART disabled. FIFOs are flushed. Clock is gated off for power savings.

1 (en): UART enabled.

PARITY_EN

Enable/disable Parity bit (9th character).

0 (dis): No Parity

1 (en): Parity enabled as 9th bit

PARITY

When PARITY_EN=1, selects odd, even, Mark or Space parity. Mark parity = always 1;

Space parity = always 0.

0 (Even): Even parity selected.

1 (ODD): Odd parity selected.

2 (MARK): Mark parity selected.

3 (SPACE): Space parity selected.

PARMD

Selects parity based on 1s or 0s count (when PARITY_EN=1).

0 (1): Parity calculation is based on number of 1s in frame.

1 (0): Parity calculation is based on number of 0s in frame.

TX_FLUSH

Flushes the TX FIFO buffer.

RX_FLUSH

Flushes the RX FIFO buffer.

BITACC

If set, bit accuracy is selected, in this case the bit duration is the same for all the bits with the optimal accuracy. But the frame duration can have a significant deviation from the expected baudrate.If clear, frame accuracy is selected, therefore bits can have different duration in order to guarantee the minimum frame deviation.

0 (FRAME): Frame accuracy.

1 (BIT): Bit accuracy.

CHAR_SIZE

Selects UART character size.

0 (5): 5 bits.

1 (6): 6 bits.

2 (7): 7 bits.

3 (8): 8 bits.

STOPBITS

Selects the number of stop bits that will be generated.

0 (1): 1 stop bit.

1 (1_5): 1.5 stop bits.

FLOW_CTRL

Enables/disables hardware flow control.

0 (dis): HW Flow Control disabled

1 (en): HW Flow Control with RTS/CTS enabled

FLOW_POL

RTS/CTS polarity.

0 (0): RTS/CTS asserted is logic 0.

1 (1): RTS/CTS asserted is logic 1.

NULL_MODEM

NULL Modem Support (RTS/CTS and TXD/RXD swap).

0 (DIS): Direct convention.

1 (EN): Null Modem Mode.

BREAK

Break control bit. It causes a break condition to be transmitted to receiving UART.

0 (DIS): Break characters are not generated.

1 (EN): Break characters are sent (all the bits are at ‘0’ including start/parity/stop).

CLKSEL

Baud Rate Clock Source Select. Selects the baud rate clock.

0 (SYSTEM): System clock.

1 (ALTERNATE): Alternate 7.3727MHz internal clock. Useful in low power modes when the system clock is slow.

RX_TO

RX Time Out. RX time out interrupt will occur after RXTO Uart characters if RX-FIFO is not empty and RX FIFO has not been read.

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