Maxim-Integrated /max32670 /GCR /CLKCTRL

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Interpret as CLKCTRL

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (div1)SYSCLK_DIV 0SYSCLK_SEL 0 (busy)SYSCLK_RDY 0 (div1)IPO_DIV 0 (dis)ERFO_EN 0 (dis)ERTCO_EN 0 (IPO_EN)IPO_EN 0 (IBRO_EN)IBRO_EN 0 (Vcor)IBRO_VS 0 (not)ERFO_RDY 0 (not)ERTCO_RDY 0 (IPO_RDY)IPO_RDY 0 (IBRO_RDY)IBRO_RDY 0 (INRO_RDY)INRO_RDY 0 (EXTCLK_RDY)EXTCLK_RDY

ERFO_RDY=not, SYSCLK_RDY=busy, ERFO_EN=dis, ERTCO_RDY=not, IBRO_VS=Vcor, ERTCO_EN=dis, SYSCLK_DIV=div1, IPO_DIV=div1

Description

Clock Control.

Fields

SYSCLK_DIV

Prescaler Select. This 3 bit field sets the system operating frequency by controlling the prescaler that divides the output of the PLL0.

0 (div1): Divide by 1.

1 (div2): Divide by 2.

2 (div4): Divide by 4.

3 (div8): Divide by 8.

4 (div16): Divide by 16.

5 (div32): Divide by 32.

6 (div64): Divide by 64.

7 (div128): Divide by 128.

SYSCLK_SEL

Clock Source Select. This 3 bit field selects the source for the system clock.

2 (ERFO): 32MHz Crystal is used for the system clock.

3 (INRO): 80kHz LIRC is used for the system clock.

4 (IPO): The internal 96 MHz oscillator is used for the system clock.

5 (IBRO): The internal 8 MHz oscillator is used for the system clock.

6 (ERTCO): 32kHz is used for the system clock.

7 (EXTCLK): External clock on gpio0 11.

SYSCLK_RDY

Clock Ready. This read only bit reflects whether the currently selected system clock source is running.

0 (busy): Switchover to the new clock source (as selected by CLKSEL) has not yet occurred.

1 (ready): System clock running from CLKSEL clock source.

IPO_DIV

Divides the HIRC96M clock before the system clock prescaler, will affect HIRC96M Autocalibration.

0 (div1): divide clock by 1

1 (div2): divide clock by 2

2 (div4): divide clock by 4

3 (div8): divide clock by 8

ERFO_EN

32MHz Crystal Oscillator Enable.

0 (dis): Is Disabled.

1 (en): Is Enabled.

ERTCO_EN

32kHz Crystal Oscillator Enable.

0 (dis): Is Disabled.

1 (en): Is Enabled.

IPO_EN

96MHz High Frequency Internal Reference Clock Enable.

IBRO_EN

8MHz High Frequency Internal Reference Clock Enable.

IBRO_VS

8MHz High Frequency Internal Reference Clock Voltage Select. This register bit is used to select the power supply to the HIRC8M.

0 (Vcor): VCore Supply

1 (1V): Dedicated 1v regulated supply.

ERFO_RDY

32MHz Crystal Oscillator Ready

0 (not): Is not Ready.

1 (ready): Is Ready.

ERTCO_RDY

32kHz Crystal Oscillator Ready

0 (not): Is not Ready.

1 (ready): Is Ready.

IPO_RDY

96MHz HIRC Ready.

IBRO_RDY

8MHz HIRC Ready.

INRO_RDY

8kHz Low Frequency Reference Clock Ready.

EXTCLK_RDY

External Clock (GPIO0[11] AF2)

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