Maxim-Integrated /max32670 /GCR /PCLKDIV

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Interpret as PCLKDIV

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (div4)AON_CLKDIV 0DIV_CLK_OUT_CTRL 0 (DIV_CLK_OUT_EN)DIV_CLK_OUT_EN

AON_CLKDIV=div4

Description

Peripheral Clock Divider.

Fields

AON_CLKDIV

Always-ON (AON) domain Clock Divider. These bits define the AON domain clock divider

0 (div4): undefined

1 (div8): undefined

2 (div16): undefined

3 (div32): undefined

DIV_CLK_OUT_CTRL

DIV_CLK_OUT Control

DIV_CLK_OUT_EN

DIV_CLK_OUT Enable

Links

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