Maxim-Integrated /max32670 /MCR /CLKDIS

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as CLKDIS

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (en)lptmr0 0 (en)lptmr1 0 (en)lpuart0

lptmr1=en, lpuart0=en, lptmr0=en

Description

Peripheral clock control register.

Fields

lptmr0

Clearing this bit will enable the low-power timer 0 (timer 4) peripheral clock.

0 (en): Enable LPTMR0 clock.

1 (dis): Disable LPTMR0 clock.

lptmr1

Clearing this bit will enable the low-power timer 1 (timer 5) peripheral clock.

0 (en): Enable LPTMR1 clock.

1 (dis): Disable LPTMR1 clock.

lpuart0

Clearing this bit will enable the low-power UART 0 (UART3) peripheral clock.

0 (en): Enable LPUART0 clock.

1 (dis): Disable LPUART0 clock.

Links

()