CLKSEL=HCLK, CLKDIV=DIV2
Clock Control Register.
| CLKSEL | Clock source select. 0 (HCLK): Select HCLK. 1 (CLK_ADC0): Select CLK_ADC0. 2 (CLK_ADC1): Select CLK_ADC1. 3 (CLK_ADC2): Select CLK_ADC2. |
| CLKDIV | Clock divider control. 0 (DIV2): Divide by 2. 1 (DIV4): Divide by 4. 2 (DIV8): Divide by 8. 3 (DIV16): Divide by 16. 4 (DIV1): Divide by 1. |