Maxim-Integrated /max32672 /GCR /PCLKDIS0

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Interpret as PCLKDIS0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (en)GPIO0 0 (GPIO1)GPIO1 0 (DMA)DMA 0 (SPI0)SPI0 0 (SPI1)SPI1 0 (SPI2)SPI2 0 (UART0)UART0 0 (UART1)UART1 0 (I2C0)I2C0 0 (CTB)CTB 0 (TMR0)TMR0 0 (TMR1)TMR1 0 (TMR2)TMR2 0 (TMR3)TMR3 0 (ADC)ADC 0 (I2C1)I2C1

GPIO0=en

Description

Peripheral Clock Disable.

Fields

GPIO0

GPIO0 Disable.

0 (en): enable it.

1 (dis): disable it.

GPIO1

GPIO1 Disable.

DMA

DMA Disable.

SPI0

SPI 0 Disable.

SPI1

SPI 1 Disable.

SPI2

SPI 2 Disable.

UART0

UART 0 Disable.

UART1

UART 1 Disable.

I2C0

I2C 0 Disable.

CTB

Crypto Disable.

TMR0

Timer 0 Disable.

TMR1

Timer 1 Disable.

TMR2

Timer 2 Disable.

TMR3

Timer 3 Disable.

ADC

ADC Clock Disable.

I2C1

I2C 1 Disable.

Links

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