AON_CLKDIV=div4, DIV_CLK_OUT_CTRL=off, DIV_CLK_OUT_EN=dis
Peripheral Clock Divider.
| AON_CLKDIV | Always-ON (AON) domain Clock Divider. These bits define the AON domain clock divider 0 (div4): undefined 1 (div8): undefined 2 (div16): undefined 3 (div32): undefined |
| DIV_CLK_OUT_CTRL | DIV_CLK_OUT Control 0 (off): HART clock off. 1 (div2): HART clock HIRC8M Div 2. 2 (div4): HART clock XO32M Div 4. 3 (div8): HART clock XO32M Div 8. |
| DIV_CLK_OUT_EN | DIV_CLK_OUT Enable 0 (dis): HART clock Disable. 1 (en): HART clock Enable. |