CHKRES=pass, SBUSARB=Fix, FPU_DIS=en, ICC0_FLUSH=normal, FLASH_PAGE_FLIP=dis, SWD_DIS=en, CCHK=complete
System Control.
| SBUSARB | System bus abritration scheme. These bits are used to select between Fixed-burst abritration and Round-Robin scheme. The Round-Robin scheme is selected by default. These bits are reset by the system reset. 0 (Fix): Fixed Burst abritration. 1 (Round): Round-robin scheme. |
| FLASH_PAGE_FLIP | . 0 (dis): Physical layout matches logical layout. 1 (en): Bottom half mapped to logical top half and vice versa. |
| FPU_DIS | Cortex M4 Floating Point Disable This bit is used to disable the floating-point unit of the Cortex-M4 0 (en): FPU Enabled. 1 (dis): FPU Disabled. |
| ICC0_FLUSH | Internal Cache Controller Flush. This bit is used to flush the code caches and the instruction buffer of the Cortex-M4. 0 (normal): Normal Code Cache Operation 1 (flush): Code Caches and CPU instruction buffer are flushed |
| CCHK | Compute ROM Checksum. This bit is self-cleared when calculation is completed. Once set, software clearing this bit is ignored and the bit will remain set until the operation is completed. 0 (complete): No operation/complete. 1 (start): Start operation. |
| SWD_DIS | Serial Wire Debug Disable. This bit is used to disable the serial wire debug interface This bit is only writeable if (FMV lock word is not programmed) or if (ICE lock word is not programmed and the ROM_DONE bit is not set) 0 (en): SWD Enabled. 1 (dis): SWD Disabled. |
| CHKRES | ROM Checksum Result. This bit is only valid when CHKRD=1. 0 (pass): ROM Checksum Correct. 1 (fail): ROM Checksum Fail. |