Maxim-Integrated /max32672 /MCR /ADC_CFG1

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as ADC_CFG1

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (dis)CH0_PU_DYN 0 (CH1_PU_DYN)CH1_PU_DYN 0 (CH2_PU_DYN)CH2_PU_DYN 0 (CH3_PU_DYN)CH3_PU_DYN 0 (CH4_PU_DYN)CH4_PU_DYN 0 (CH5_PU_DYN)CH5_PU_DYN 0 (CH6_PU_DYN)CH6_PU_DYN 0 (CH7_PU_DYN)CH7_PU_DYN 0 (CH8_PU_DYN)CH8_PU_DYN 0 (CH9_PU_DYN)CH9_PU_DYN 0 (CH10_PU_DYN)CH10_PU_DYN 0 (CH11_PU_DYN)CH11_PU_DYN 0 (CH12_PU_DYN)CH12_PU_DYN

CH0_PU_DYN=dis

Description

ADC Config Register1.

Fields

CH0_PU_DYN

ADC PU Dynamic Control for CH0

0 (dis): divider select always used.

1 (en): divider select only used when channel is selected.

CH1_PU_DYN

ADC PU Dynamic Control for CH1

CH2_PU_DYN

ADC PU Dynamic Control for CH2

CH3_PU_DYN

ADC PU Dynamic Control for CH3

CH4_PU_DYN

ADC PU Dynamic Control for CH4

CH5_PU_DYN

ADC PU Dynamic Control for CH5

CH6_PU_DYN

ADC PU Dynamic Control for CH6

CH7_PU_DYN

ADC PU Dynamic Control for CH7

CH8_PU_DYN

ADC PU Dynamic Control for CH8

CH9_PU_DYN

ADC PU Dynamic Control for CH9

CH10_PU_DYN

ADC PU Dynamic Control for CH10

CH11_PU_DYN

ADC PU Dynamic Control for CH11

CH12_PU_DYN

ADC PU Dynamic Control for CH12

Links

()