Maxim-Integrated /max32672 /MCR /LPPIOCTRL

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Interpret as LPPIOCTRL

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (LPTMR0_I)LPTMR0_I 0 (LPTMR0_O)LPTMR0_O 0 (LPTMR1_I)LPTMR1_I 0 (LPTMR1_O)LPTMR1_O 0 (LPUART0_RX)LPUART0_RX 0 (LPUART0_TX)LPUART0_TX 0 (LPUART0_CTS)LPUART0_CTS 0 (LPUART0_RTS)LPUART0_RTS

Description

Low Power Peripheral IO Control Register.

Fields

LPTMR0_I

Enable control for LPTMR0 input.

LPTMR0_O

Enable control for LPTMR0 output.

LPTMR1_I

Enable control for LPTMR1 input.

LPTMR1_O

Enable control for LPTMR1 output.

LPUART0_RX

Enable control for LPUART0 RX.

LPUART0_TX

Enable control for LPUART0 TX.

LPUART0_CTS

Enable control for LPUART0 CTS.

LPUART0_RTS

Enable control for LPUART0 RTS.

Links

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