BG_DIS=on, RAM3RET_EN=dis, RAM0RET_EN=dis, RAM1RET_EN=dis, FVDDEN=dis, FASTWK_EN=dis, VBBMON_DIS=en, LDO_DIS=en, RETREG_EN=dis, VCORE_DET_BYPASS=en, VCORE_EXT=dis, VDDAMON_DIS=en, VCOREPOR_DIS=en, VCOREMON_DIS=en, OVR=0_9V, RAM2RET_EN=dis, STORAGE_EN=dis, PORVDDMON_DIS=dis
Low Power Control Register.
| RAM0RET_EN | System RAM retention in BACKUP mode. These two bits are used in conjuction with RREGEN bit. 0 (dis): Disable Ram Retention. 1 (en): Enable System RAM 0 retention. |
| RAM1RET_EN | System RAM retention in BACKUP mode. These two bits are used in conjuction with RREGEN bit. 0 (dis): Disable Ram Retention. 1 (en): Enable System RAM 1 retention. |
| RAM2RET_EN | System RAM retention in BACKUP mode. These two bits are used in conjuction with RREGEN bit. 0 (dis): Disable Ram Retention. 1 (en): Enable System RAM 2 retention. |
| RAM3RET_EN | System RAM retention in BACKUP mode. These two bits are used in conjuction with RREGEN bit. 0 (dis): Disable Ram Retention. 1 (en): Enable System RAM 3 retention. |
| OVR | Operating Voltage Range 0 (0_9V): 0.9V 12MHz 1 (1_0V): 1.0V 48MHz 2 (1_1V): 1.1V 96MHz |
| VCORE_DET_BYPASS | Block Auto-Detect 0 (en): enable 1 (dis): disable |
| FVDDEN | Flash VDD Enable, force the flash VDD to remain enabled during LP modes. 0 (dis): enable 1 (en): disable |
| RETREG_EN | Retention Regulator Enable. This bit controls the retention regulator in BACKUP mode. 0 (dis): Disabled. 1 (en): Enabled. |
| STORAGE_EN | STORAGE Mode ENable. This bit allows low-power background mode operations, while the CPU is in DeepSleep. 0 (dis): Disabled. 1 (en): Enabled. |
| FASTWK_EN | Fast Wake-Up Mode. This bit enables fast wake-up from DeepSleep mode. (5uS typical). 0 (dis): Disabled. 1 (en): Enabled. |
| BG_DIS | Bandgap OFF. This controls the System Bandgap in DeepSleep mode. 0 (on): Bandgap is always ON. 1 (off): Bandgap is OFF in DeepSleep mode (default). |
| VCOREPOR_DIS | VDDC (Vcore) Power on reset Monitor Disable.This bit controls the Power-On Reset monitor on VDDC supply in DeepSleep and BACKUP mode. 0 (en): Enable 1 (dis): Disabled. |
| LDO_DIS | Disable Main LDO 0 (en): Enable 1 (dis): Disabled. |
| VCORE_EXT | Use external VCORE for 1V supply 0 (dis): disable 1 (en): use Vcore for retention. |
| VCOREMON_DIS | VDDC (Vcore) Monitor Disable. This bit controls the power monitor on the VCore supply in all operating modes. 0 (en): Enable 1 (dis): Disabled. |
| VDDAMON_DIS | VDDA Monitor Disable. This bit controls the power monitor of the Analog Supply in all operating modes. 0 (en): Enable if Bandgap is ON (default) 1 (dis): Disabled. |
| PORVDDMON_DIS | VDDIO Power-On Reset Monitor Disable. This bit controls the Power-On Reset monitor on VDDIO supply in all operating mods. 0 (dis): Disabled. 1 (en): Enabled. |
| VBBMON_DIS | VBB Monitor Disable. This bit controls the power monitor of the Analog Supply in all operating modes. 0 (en): Enable if Bandgap is ON (default) 1 (dis): Disabled. |
| INRO_EN | INRO remains on in all power modes if this bit is set otherwise it is controled by the LP controller |
| ERTCO_EN | XRTCO remains on in all power modes if this bit is set otherwise it is controled by the LP controller |
| TM_LPMODE | TBD |
| TM_PWRSEQ | TBD |