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Maxim-Integrated /max32672 /UART /CLKDIV

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Interpret as CLKDIV

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0CLKDIV

Description

Clock Divider register

Fields

CLKDIV

Baud rate divisor value

Links

()

Register Reference

https://github.com/analogdevicesinc/msdk