Regviz

Maxim-Integrated /max32675 /FLC /CTRL

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as CTRL

Share

Cut and paste this URL to share the unmodified register and value:

https://regviz.com/r/Maxim-Integrated/max32672/FLC/CTRL#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (complete)WR 0 (ME)ME 0 (PGE)PGE 0 (nop)ERASE_CODE0 (idle)PEND 0 (LVE)LVE 0UNLOCK

ERASE_CODE=nop, WR=complete, PEND=idle

Description

Flash Control Register.

Fields

WR

Write. This bit is automatically cleared after the operation.

0 (complete): No operation/complete.

1 (start): Start operation.
ME

Mass Erase. This bit is automatically cleared after the operation.
PGE

Page Erase. This bit is automatically cleared after the operation.
ERASE_CODE

Erase Code. The ERASE_CODE must be set up property before erase operation can be initiated. These bits are automatically cleared after the operation is complete.

0 (nop): No operation.

85 (erasePage): Enable Page Erase.

170 (eraseAll): Enable Mass Erase. The debug port must be enabled.
PEND

Flash Pending. When Flash operation is in progress (busy), Flash reads and writes will fail. When PEND is set, write to all Flash registers, with exception of the Flash interrupt register, are ignored.

0 (idle): Idle.

1 (busy): Busy.
LVE

Low Voltage enable.
UNLOCK

Flash Unlock. The correct unlock code must be written to these four bits before any Flash write or erase operation is allowed.

2 (unlocked): Flash Unlocked.

3 (locked): Flash Locked.

Links

()

Register Reference

https://github.com/analogdevicesinc/msdk