Maxim-Integrated /max78000 /GCR /PM

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Interpret as PM

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (active)MODE0 (dis)GPIO_WE 0 (RTC_WE)RTC_WE 0 (WUT_WE)WUT_WE 0 (AINCOMP_WE)AINCOMP_WE 0 (active)ISO_PD 0 (IPO_PD)IPO_PD 0 (IBRO_PD)IBRO_PD

ISO_PD=active, GPIO_WE=dis, MODE=active

Description

Power Management.

Fields

MODE

Operating Mode. This two bit field selects the current operating mode for the device. Note that code execution only occurs during ACTIVE mode.

0 (active): Active Mode.

1 (sleep): Cortex-M4 Active, RISC-V Sleep Mode.

2 (standby): Standby Mode.

4 (backup): Backup Mode.

8 (lpm): LPM or CM4 Deep Sleep Mode.

9 (upm): UPM.

10 (powerdown): Power Down Mode.

GPIO_WE

GPIO Wake Up Enable. This bit enables all GPIO pins as potential wakeup sources. Any GPIO configured for wakeup is capable of causing an exit from IDLE or STANDBY modes when this bit is set.

0 (dis): Wake Up Disable.

1 (en): Wake Up Enable.

RTC_WE

RTC Alarm Wake Up Enable. This bit enables RTC alarm as wakeup source. If enabled, the desired RTC alarm must be configured via the RTC control registers.

WUT_WE

WUT Wake Up Enable. This bit enables the Wake-Up Timer as wakeup source.

AINCOMP_WE

AIN COMP Wake Up Enable. This bit enables AIN COMP as wakeup source.

ISO_PD

60 MHz power down. This bit selects the 60 MHz clock power state in DEEPSLEEP mode.

0 (active): Mode is Active.

1 (deepsleep): Powered down in DEEPSLEEP.

IPO_PD

100 MHz power down. This bit selects 100 MHz clock power state in DEEPSLEEP mode.

IBRO_PD

7.3725 MHz power down. This bit selects 7.3725 MHz clock power state in DEEPSLEEP mode.

Links

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