RX D-PHY Interrupt Enable Register.
| DL0STOP | DPHY Data Lane0 Stop State (ppi_stopstate_lan0) interrupt enable. |
| DL1STOP | DPHY Data Lane1 Stop State (ppi_stopstate_lan1) interrupt enable. |
| CL0STOP | DPHY Clock Lane0 Stop State (ppi_stopstate_clk0) interrupt enable. |
| DL0ECONT0 | DPHY Data Lane0 LP0 Contention Error (ppi_errcontentionp0_lan0) interrupt enable |
| DL0ECONT1 | DPHY Data Lane0 LP1 Contention Error (ppi_errcontentionp1_lan0) interrupt enable |
| DL0ESOT | DPHY Data Lane0 Start-of-Transmission (SoT) Error (ppi_errsoths_lan0) interrupt enable |
| DL1ESOT | DPHY Data Lane1 Start-of-Transmission (SoT) Error (ppi_errsoths_lan1) interrupt enable |
| DL0ESOTS | DPHY Data Lane0 SOT Synchronization Error (ppi_errsotsynchs_lan0) interrupt enable |
| DL1ESOTS | DPHY Data Lane1 SOT Synchronization Error (ppi_errsotsynchs_lan1) interrupt enable |
| DL0EESC | DPHY Data Lane0 Escape Entry Error (ppi_erresc_lan0) interrupt enable |
| DL1EESC | DPHY Data Lane1 Escape Entry Error (ppi_erresc_lan1) interrupt enable |
| DL0ESESC | DPHY Data Lane0 Low-Power Data Transmission Synchronization Error (ppi_errsyncesc_lan0) interrupt enable |
| DL1ESESC | DPHY Data Lane1 Low-Power Data Transmission Synchronization Error (ppi_errsyncesc_lan0) interrupt enable |
| DL0ECTL | DPHY Data Lane0 Control Error (ppi_errcontrol_lan0) interrupt enable |
| DL1ECTL | DPHY Data Lane1 Control Error (ppi_errcontrol_lan0) interrupt enable |