Maxim-Integrated /max78002 /CSI2 /RX_EINT_PPI_IF

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Interpret as RX_EINT_PPI_IF

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (DL0STOP)DL0STOP 0 (DL1STOP)DL1STOP 0 (CL0STOP)CL0STOP 0 (DL0ECONT0)DL0ECONT0 0 (DL0ECONT1)DL0ECONT1 0 (DL0ESOT)DL0ESOT 0 (DL1ESOT)DL1ESOT 0 (DL0ESOTS)DL0ESOTS 0 (DL1ESOTS)DL1ESOTS 0 (DL0EESC)DL0EESC 0 (DL1EESC)DL1EESC 0 (DL0ESESC)DL0ESESC 0 (DL1ESESC)DL1ESESC 0 (DL0ECTL)DL0ECTL 0 (DL1ECTL)DL1ECTL

Description

RX D-PHY Interrupt Flag Register.

Fields

DL0STOP

DPHY Data Lane0 Stop State (ppi_stopstate_lan0) interrupt flag.

DL1STOP

DPHY Data Lane1 Stop State (ppi_stopstate_lan1) interrupt flag.

CL0STOP

DPHY Clock Lane0 Stop State (ppi_stopstate_clk0) interrupt flag.

DL0ECONT0

DPHY Data Lane0 LP0 Contention Error (ppi_errcontentionp0_lan0) interrupt flag

DL0ECONT1

DPHY Data Lane0 LP1 Contention Error (ppi_errcontentionp1_lan0) interrupt flag

DL0ESOT

DPHY Data Lane0 Start-of-Transmission (SoT) Error (ppi_errsoths_lan0) interrupt flag

DL1ESOT

DPHY Data Lane1 Start-of-Transmission (SoT) Error (ppi_errsoths_lan1) interrupt flag

DL0ESOTS

DPHY Data Lane0 SOT Synchronization Error (ppi_errsotsynchs_lan0) interrupt flag

DL1ESOTS

DPHY Data Lane1 SOT Synchronization Error (ppi_errsotsynchs_lan1) interrupt flag

DL0EESC

DPHY Data Lane0 Escape Entry Error (ppi_erresc_lan0) interrupt flag

DL1EESC

DPHY Data Lane1 Escape Entry Error (ppi_erresc_lan1) interrupt flag

DL0ESESC

DPHY Data Lane0 Low-Power Data Transmission Synchronization Error (ppi_errsyncesc_lan0) interrupt flag

DL1ESESC

DPHY Data Lane1 Low-Power Data Transmission Synchronization Error (ppi_errsyncesc_lan0) interrupt flag

DL0ECTL

DPHY Data Lane0 Control Error (ppi_errcontrol_lan0) interrupt flag

DL1ECTL

DPHY Data Lane1 Control Error (ppi_errcontrol_lan0) interrupt flag

Links

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