Maxim-Integrated /max78002 /DVS /CTL

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as CTL

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (MON_ENA)MON_ENA 0 (ADJ_ENA)ADJ_ENA 0 (PS_FB_DIS)PS_FB_DIS 0 (CTRL_TAP_ENA)CTRL_TAP_ENA 0PROP_DLY 0 (MON_ONESHOT)MON_ONESHOT 0 (GO_DIRECT)GO_DIRECT 0 (DIRECT_REG)DIRECT_REG 0 (PRIME_ENA)PRIME_ENA 0 (LIMIT_IE)LIMIT_IE 0 (RANGE_IE)RANGE_IE 0 (ADJ_IE)ADJ_IE 0REF_SEL0INC_VAL 0 (DVS_PS_APB_DIS)DVS_PS_APB_DIS 0 (DVS_HI_RANGE_ANY)DVS_HI_RANGE_ANY 0 (FB_TO_IE)FB_TO_IE 0 (FC_LV_IE)FC_LV_IE 0 (PD_ACK_ENA)PD_ACK_ENA 0 (ADJ_ABORT)ADJ_ABORT

Description

Control Register

Fields

MON_ENA

Enable the DVS monitoring circuit

ADJ_ENA

Enable the power supply adjustment based on measurements

PS_FB_DIS

Power Supply Feedback Disable

CTRL_TAP_ENA

Use the TAP Select for automatic adjustment or monitoring

PROP_DLY

Additional delay to monitor lines

MON_ONESHOT

Measure delay once

GO_DIRECT

Operate in automatic mode or move directly

DIRECT_REG

Step incrementally to target voltage

PRIME_ENA

Include a delay line priming signal before monitoring

LIMIT_IE

Enable Limit Error Interrupt

RANGE_IE

Enable Range Error Interrupt

ADJ_IE

Enable Adjustment Error Interrupt

REF_SEL

Select TAP used for voltage adjustment

INC_VAL

Step size to increment voltage when in automatic mode

DVS_PS_APB_DIS

Prevent the application code from adjusting Vcore

DVS_HI_RANGE_ANY

Any high range signal from a delay line will cause a voltage adjustment

FB_TO_IE

Enable Voltage Adjustment Timeout Interrupt

FC_LV_IE

Enable Low Voltage Interrupt

PD_ACK_ENA

Prevent DVS from ackā€™ing a request to enter a low power mode until in the idle state

ADJ_ABORT

Causes the DVS to enter the idle state immediately on a request to enter a low power mode

Links

()