Maxim-Integrated /max78002 /GCR /PCLKDIS1

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Interpret as PCLKDIS1

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (en)UART2 0 (TRNG)TRNG 0 (SMPHR)SMPHR 0 (SDHC)SDHC 0 (OWM)OWM 0 (CRC)CRC 0 (AES)AES 0 (SPI0)SPI0 0 (PCIF)PCIF 0 (I2S)I2S 0 (I2C2)I2C2 0 (WDT0)WDT0 0 (CSI2)CSI2 0 (CPU1)CPU1

UART2=en

Description

Peripheral Clock Disable.

Fields

UART2

UART2 Clock Disable.

0 (en): Enable.

1 (dis): Disable.

TRNG

TRNG Clock Disable.

SMPHR

SMPHR Clock Disable.

SDHC

SDHC Clock Disable.

OWM

One-Wire Clock Disable.

CRC

CRC Clock Disable.

AES

AES Clock Disable.

SPI0

SPI0 AHB.

PCIF

Parallel Camera Interface Clock Disable.

I2S

I2S Clock Disable.

I2C2

I2C2 Clock Disable.

WDT0

Watch Dog Timer 0 Clock Disable.

CSI2

CSI2 Clock Disable.

CPU1

CPU1 Clock Disable.

Links

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