SDIOCLKDIV=IPO_DIV2, CNNCLKSEL=PCLK, CNNCLKDIV=div2
Peripheral Clock Divider.
| SDIOCLKDIV | 0 (IPO_DIV2): 48 MHz 1 (IPO_DIV4): 24 MHz |
| CNNCLKDIV | CNN Clock Divider. 0 (div2): undefined 1 (div4): undefined 2 (div8): undefined 3 (div16): undefined 4 (div1): undefined |
| CNNCLKSEL | CNN Clock Select. 0 (PCLK): undefined 1 (ISO): undefined 3 (IPLL): undefined |