Clock Divider Number Register
| HCLK_N | HCLK clock divide number from HCLK clock source The HCLK clock frequency = (HCLK clock source frequency) / (HCLK_N + 1) |
| UART_N | UART clock divide number from UART clock source The UART clock frequency = (UART clock source frequency ) / (UART_N + 1) |
| ADC_N | ADC clock divide number from ADC clock source The ADC clock frequency = (ADC clock source frequency ) / (ADC_N + 1) |