Nuvoton /M05x_registers /CLK /CLKSTATUS

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Interpret as CLKSTATUS

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (XTL12M_STB)XTL12M_STB 0 (PLL_STB)PLL_STB 0 (OSC10K_STB)OSC10K_STB 0 (OSC22M_STB)OSC22M_STB 0 (CLK_SW_FAIL)CLK_SW_FAIL

Description

Clock status monitor Register

Fields

XTL12M_STB

XTL12M clock source stable flag 1 = External Crystal clock is stable 0 = External Crystal clock is not stable or not enable

PLL_STB

PLL clock source stable flag 1 = PLL clock is stable 0 = PLL clock is not stable or not enable

OSC10K_STB

OSC10K clock source stable flag 1 = OSC10K clock is stable 0 = OSC10K clock is not stable or not enable

OSC22M_STB

OSC22M clock source stable flag 1 = OSC22M clock is stable 0 = OSC22M clock is not stable or not enable

CLK_SW_FAIL

Clock switch fail flag 1 = Clock switch fail 0 = Clock switch success This bit will be set when target switch clock source is not stable. Write 1 to clear this bit to zero.

Links

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