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Nuvoton /M05x_registers /CLK /FRQDIV

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Interpret as FRQDIV

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0FSEL0 (DIVIDER_EN)DIVIDER_EN

Description

Frequency Divider Control Register

Fields

FSEL

Divider Output Frequency Selection Bits The formula of output frequency is Fout = Fin/2(N+1), where Fin is the input clock frequency, Fout is the frequency of divider output clock, N is the 4-bit value of FSEL[3:0].
DIVIDER_EN

Frequency Divider Enable Bit 0 = Disable Frequency Divider 1 = Enable Frequency Divider

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data