PLL Control Register
| FB_DV | PLL Feedback Divider Control Pins (PLL_F[8:0]) |
| IN_DV | PLL Input Divider Control Pins (PLL_R[4:0]) |
| OUT_DV | PLL Output Divider Control Pins (PLL_OD[1:0]) |
| PD | Power Down Mode. If set the IDLE bit “1” in PWRCON register, the PLL will enter power down mode too 0 = PLL is in normal mode (default) 1 = PLL is in power-down mode |
| BP | PLL Bypass Control 0 = PLL is in normal mode (default) 1 = PLL clock output is same as clock input (XTALin) |
| OE | PLL OE (FOUT enable) pin Control 0 = PLL FOUT enable 1 = PLL FOUT is fixed low |
| PLL_SRC | PLL Source Clock Select 1 = PLL source clock from 22.1184 MHz oscillator 0 = PLL source clock from external crystal clock (4 ~ 24 MHz) |