System Power Down Control Register
| XTL12M_EN | External Crystal Oscillator Control The bit default value is set by flash controller user configuration register config0 [26:24]. When the default clock source is from external crystal. The bit is auto set to “1” 1 = Crystal oscillation enable 0 = Crystal oscillation disable |
| OSC22M_EN | Internal 22.1184 MHz Oscillator Control 1 = 22.1184 MHz Oscillation enable 0 = 22.1184 MHz Oscillation disable |
| OSC10K_EN | Internal 10KHz Oscillator Control 1 = 10KHz Oscillation enable 0 = 10KHz Oscillation disable |
| PD_WU_DLY | Enable the wake up delay counter. When the chip wakes up from power down mode, the clock control will delay certain clock cycles to wait system clock stable. The delayed clock cycle is 4096 clock cycles when chip work at external crystal (4 ~ 24MHz), and 256 clock cycles when chip work at 22.1184 MHz oscillator. 1 = Enable the clock cycle delay 0 = Disable the clock cycle delay |
| PD_WU_INT_EN | Power down mode wake Up Interrupt Enable 0 = Disable 1 = Enable. The interrupt will occur when Power down mode (Deep Sleep Mode) wakeup. |
| PD_WU_STS | Chip power down wake up status flag Set by “power down wake up”, it indicates that resume from power down mode The flag is set if the GPIO(P0~P4), UART wakeup Write 1 to clear the bit Note: This bit is working only if PD_WU_INT_EN (PWRCON[5]) set to 1. |
| PWR_DOWN_EN | System power down enable bit When set this bit “1”, the chip power down mode is enabled and the chip power down active is depend on the PD_WAIT_CPU bit (a) if the PD_WAIT_CPU is “0” then the chip power down after the PWR_DOWN_EN bit set. (b) if the PD_WAIT_CPU is “1” then the chip keep active till the CPU sleep mode also active and then the chip power down When chip wake up from power down, this bit is auto cleared, user need to set this bit again for next power down. When in power down mode, external crystal (4~ 24MHz) and the 22.1184 MHz OSC will be disabled in this mode, but the 10 kHz OSC is not controlled by power down mode. When in power down mode, the PLL and system clock are disabled, and ignored the clock source selection. The clocks of peripheral are not controlled by power down mode, if the peripheral clock source is from 10 kHz oscillator. 1 = Chip enter the power down mode instant or wait CPU sleep command WFI 0 = Chip operate in normal mode or CPU in idle mode (sleep mode) because of WFI command |
| PD_WAIT_CPU | This bit control the power down entry condition 1 = Chip entry power down mode when the both PWR_DOWN and CPU run WFI instruction. 0 = Chip entry power down mode when the PWR_DOWN bit is set to 1 |