External Bus Interface 0 Timing Control Register
| ExttACC | EBI Data Accesss Time ExttACC define data access time (tACC). tACC = (ExttACC + 1) * MCLK |
| ExttAHD | EBI Data Access Hold Time ExttAHD define data access hold time (tAHD). tAHD = (ExttAHD + 1) * MCLK |
| ExtIW2X | Idle State Cycle After Write When write action is finish, idle state is inserted and nCS return to high if ExtIW2X is not zero. Idle state cycle = (ExtIW2X * MCLK) |
| ExtIR2R | Idle State Cycle Between Read-Read When read action is finish and next action is going to read, idle state is inserted and nCS return to high if ExtIR2R is not zero. Idle state cycle = (ExtIR2R * MCLK) |