IP Reset Control Resister1
| CHIP_RST | CHIP one shot reset. Set this bit will reset the CHIP, including CPU kernel and all peripherals, and this bit will automatically return to “0” after the 2 clock cycles. The CHIP_RST is same as the POR reset , all the chip module is reset and the chip setting from flash are also reload This bit is the protected bit, program this need an open lock sequence, write “59h”,“16h”,“88h” to address 0x5000_0100 to un-lock this bit. Reference the register REGWRPROT at address GCR_BA + 0x100 0= Normal 1= Reset CHIP |
| CPU_RST | CPU kernel one shot reset. Set this bit will reset the Cortex-M0 CPU kernel and Flash memory controller (FMC). This bit will automatically return to “0” after the 2 clock cycles This bit is the protected bit, program this need an open lock sequence, write “59h”,“16h”,“88h” to address 0x5000_0100 to un-lock this bit. Reference the register REGWRPROT at address GCR_BA + 0x100 0= Normal 1= Reset CPU |
| EBI_RST | EBI Controller Reset Set these bit “1” will generate a reset signal to the EBI. User need to set this bit to “0” to release from the reset state This bit is the protected bit, program this need an open lock sequence, write “59h”,“16h”,“88h” to address 0x5000_0100 to un-lock this bit. Reference the register REGWRPROT at address GCR_BA + 0x100 0= Normal operation 1= EBI IP reset |