Nuvoton /M05x_registers /GCR /P0_MFP

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Interpret as P0_MFP

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0P0_MFP0 (P0_ALT0)P0_ALT0 0 (P0_ALT1)P0_ALT1 0 (P0_ALT2)P0_ALT2 0 (P0_ALT3)P0_ALT3 0 (P0_ALT4)P0_ALT4 0 (P0_ALT5)P0_ALT5 0 (P0_ALT6)P0_ALT6 0 (P0_ALT7)P0_ALT7 0P0_TYPEn

Description

P0 multiple function and input type control register

Fields

P0_MFP

P0 multiple function Selection The pin function of P0 is depending on P0_MFP and P0_ALT. Refer to P0_ALT descriptions in detail.

P0_ALT0

P0.0 alternate function Selection The pin function of P0.0 is depend on P0_MFP[0] and P0_ALT[0]. P0_ALT[0] P0_MFP[0] P0.0function 0 0 P0.0 0 1 AD0(EBI) 1 0 CTS1(UART1) 1 1 Reserved

P0_ALT1

P0.1 alternate function Selection The pin function of P0.1 is depend on P0_MFP[1] and P0_ALT[1]. P0_ALT[1] P0_MFP[1] P0.1function 0 0 P0.1 0 1 AD1(EBI) 1 0 RTS1(UART1) 1 1 Reserved

P0_ALT2

P0.2 alternate function Selection The pin function of P0.2 is depend on P0_MFP[2] and P0_ALT[2]. P0_ALT[2] P0_MFP[2] P0.2function 0 0 P0.2 0 1 AD2(EBI) 1 0 CTS0(UART0) 1 1 Reserved

P0_ALT3

P0.3 alternate function Selection The pin function of P0.3 is depend on P0_MFP[3] and P0_ALT[3]. P0_ALT[3] P0_MFP[3] P0.3function 0 0 P0.3 0 1 AD3(EBI) 1 0 RTS0(UART0) 1 1 Reserved

P0_ALT4

P0.4 alternate function Selection The pin function of P0.4 is depend on P0_MFP[4] and P0_ALT[4]. P0_ALT[4] P0_MFP[4] P0.4function 0 0 P0.4 0 1 AD4(EBI) 1 0 SPISS1(SPI1) 1 1 Reserved

P0_ALT5

P0.5 alternate function Selection The pin function of P0.5 is depend on P0_MFP[5] and P0_ALT[5]. P0_ALT[5] P0_MFP[5] P0.5 function 0 0 P0.5 0 1 AD5(EBI) 1 0 MOSI_1(SPI1) 1 1 Reserved

P0_ALT6

P0.6 alternate function Selection The pin function of P0.6 is depend on P0_MFP[6] and P0_ALT[6]. P0_ALT[6] P0_MFP[6] P0.6 function 0 0 P0.6 0 1 AD6(EBI) 1 0 MISO_1(SPI1) 1 1 Reserved

P0_ALT7

P0.7 alternate function Selection The pin function of P0.7 is depend on P0_MFP[7] and P0_ALT[7]. P0_ALT[7] P0_MFP[7] P0.7 function 0 0 P0.7 0 1 AD7(EBI) 1 0 SPICLK1(SPI1) 1 1 Reserved

P0_TYPEn

P0[7:0] input Schmitt Trigger function Enable 1= P0[7:0] I/O input Schmitt Trigger function enable 0= P0[7:0] I/O input Schmitt Trigger function disable

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