System Reset Source Register
| RSTS_POR | The RSTS_POR flag is set by the “reset signal” which is from the Power-On Reset (POR) module or bit CHIP_RST (IPRSTC1[0]) is set, to indicate the previous reset source. 1= The Power-On-Reset(POR) or CHIP_RST=1 had issued the reset signal to reset the system. 0= No reset from POR This bit is cleared by writing 1 to itself. |
| RSTS_RESET | The RSTS_RESET flag is set by the “reset signal” from the /RESET pin to indicate the previous reset source. 1= The Pin /RESET had issued the reset signal to reset the system. 0= No reset from Pin /RESET This bit is cleared by writing 1 to itself. |
| RSTS_WDT | The RSTS_WDT flag is set by the “reset signal” from the Watch Dog Timer to indicate the previous reset source. 1= The Watch Dog Timer had issued the reset signal to reset the system. 0= No reset from Watch-Dog This bit is cleared by writing 1 to itself. |
| RSTS_LVR | The RSTS_LVR flag is set by the “reset signal” from the Low-Voltage-Reset module to indicate the previous reset source. 1= The LVR module had issued the reset signal to reset the system. 0= No reset from LVR This bit is cleared by writing 1 to itself. |
| RSTS_BOD | The RSTS_BOD flag is set by the “reset signal” from the Brown-Out-Detected module to indicate the previous reset source. 1= The Brown-Out-Detected module had issued the reset signal to reset the system. 0= No reset from BOD This bit is cleared by writing 1 to itself. |
| RSTS_MCU | The RSTS_MCU flag is set by the “reset signal” from the MCU Cortex_M0 kernel to indicate the previous reset source. 1= The MCU Cortex_M0 had issued the reset signal to reset the system by software writing 1 to bit SYSRESTREQ(AIRCR[2], Application Interrupt and Reset Control Register) in system control registers of Cortex_M0 kernel. 0= No reset from MCU This bit is cleared by writing 1 to itself. |
| RSTS_CPU | The RSTS_CPU flag is set by hardware if software writes CPU_RST (IPRSTC1[1]) with a “1” to rest Cortex-M0 CPU kernel and Flash memory controller(FMC). 1= The Cortex-M0 CPU kernel and FMC are reset by software set CPU_RST to 1. 0= No reset from CPU This bit is cleared by writing 1 to itself. |