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Nuvoton /M05x_registers /I2C /I2CLK

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Interpret as I2CLK

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0I2CLK

Description

I2C clock divided Register

Fields

I2CLK

I2C clock divided Register The I2C clock rate bits: Data Baud Rate of I2C = PCLK /(4x(I2CLK+1)).

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data