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Nuvoton /M05x_registers /PWMA /PIIR

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Interpret as PIIR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (PWMIF0)PWMIF0 0 (PWMIF1)PWMIF1 0 (PWMIF2)PWMIF2 0 (PWMIF3)PWMIF3

Description

PWM Interrupt Indication Register

Fields

PWMIF0

PWM channel 0 Interrupt Status Flag is set by hardware when PWM0 down counter reaches zero, software can clear this bit by writing a one to it.
PWMIF1

PWM channel 1 Interrupt Status Flag is set by hardware when PWM1 down counter reaches zero, software can clear this bit by writing a one to it.
PWMIF2

PWM channel 2 Interrupt Status Flag is set by hardware when PWM2 down counter reaches zero, software can clear this bit by writing a one to it.
PWMIF3

PWM channel 3 Interrupt Status Flag is set by hardware when PWM3 down counter reaches zero, software can clear this bit by writing a one to it.

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data