Slave Select Register
| SSR | Slave Select Register (master only) If AUTOSS bit is cleared, writing 1 to this bit sets the SPISSx line to active state and writing 0 sets the line back to inactive state. If AUTOSS bit is set, writing 1 to this bit will select the SPISSx line to be automatically driven to active state for the duration of the transmit/receive, and will be driven to inactive state for the rest of the time. (The active level of SPISSx0/1 is specified in SS_LVL). |
| SS_LVL | Slave Select Active Level It defines the active level of slave select signal (SPISSx). 1 = The slave select signal SPISSx is active at high-level/rising-edge. 0 = The slave select signal SPISSx is active at low-level/falling-edge. |
| AUTOSS | Automatic Slave Select (master only) 1 = If this bit is set, SPISSx signal is generated automatically. It means that slave select signal will be asserted by the SPI controller when transmit/receive is started by setting GO_BUSY, and is de-asserted after each transmit/receive is finished. 0 = If this bit is cleared, slave select signal will be asserted and de-asserted by setting and clearing SSR[0]. |
| SS_LTRIG | Slave Select Level Trigger (slave only) 1: The slave select signal will be level-trigger. It depends on SS_LVL to decide the signal is active low or active high. 0: The input slave select signal is edge-trigger. This is default value. |
| LTRIG_FLAG | Level Trigger Flag When the SS_LTRIG bit is set in slave mode, this bit can be read to indicate the received bit number is met the requirement or not. 1 = The transaction number and the transferred bit length met the specified requirements which defined in TX_NUM and TX_BIT_LEN. 0 = The transaction number or the transferred bit length of one transaction doesn’t meet the specified requirements. Note: This bit is READ only |