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Nuvoton /M05x_registers /TMR0 /TDR

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Interpret as TDR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0TDR

Description

Timer0 Data Register

Fields

TDR

Timer Data Register When TCSR.TDR_EN is set to 1, the internal 24-bit up-timer value will be loaded into TDR. User can read this register for the up-timer value.

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data